Abstract

Physical mechanisms that dominate the electrostatic discharge (ESD) robustness of silicon-on-insulator (SOI) devices are theoretically and experimentally investigated here. The authors experimentally find that the ESD robustness depends strongly on the device geometry correlated turn on mechanism. Moreover, the punchthrough mechanism is theoretically demonstrated to be the unsuitable turn on mechanism that causes a nonuniform current distribution and a low ESD strength. The punchthrough mechanism, according to their theoretical analysis, will occur in scaled down structure and reduce the benefits arising from sizing down. Therefore, optimization of a device structure is necessary to prevent nanoscaled SOI devices from the punchthrough induced ESD robustness degradation.

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