Pulse optimization and device engineering of 3D charge-trap flash for synaptic operation

Abstract

We investigate 3D charge-trap (CT) nand flash cells using device-physics based multi-scale simulations to explore their potential and optimum operating conditions as electronic synapses of the neuromorphic hardware. A set of figure of merits (FOMs) has been adopted to indicate their goodness of operation under incremental pulse inputs. The results of this study suggest that excellent synaptic FOMs can be attained from 3D CT nands by designing and calibrating the input pulse trains. The impact of variations of device dimensions on charge capture and release phenomena have been investigated and linked to output characteristics in order to obtain intuitive guidelines for attaining desired synaptic functionalities. By co-designing gate dielectric stack and input pulses, the threshold voltage (VT) of the 3D CT cell can be sequentially increased and decreased in a linear and symmetric fashion, providing a large number of distinct VT levels with good retention characteristics. Statistical simulations suggest that device-to-device variations of electrical responses have a negligible impact on the synaptic capabilities of these devices. It has also been shown that the incorporation of deeper traps through material engineering improves synaptic reliability of the 3D CT cells under prolonged operations.