Pseudo-MOS Operation of Ultra-Narrow Polycrystalline Silicon Wires: Electrical Characterization and Memory Effects

Abstract

AbstractThis paper presents a new method for the electrical characterization of polycrystalline silicon wires based on the pseudo-MOS effect. The investigated devices are ultra-narrow (0.1- 0.2μm), four-contact polycrystalline silicon wires composed of several individual grains in series. The pseudo-MOS static operation allow the examination of interface and bulk characteristics via MOSFET modeling in terms of electrical parameters (carrier mobility, flat band and threshold voltages, mobility reduction coefficient). Additionally, the measurement of 1/f noise is shown to be a useful complementary characterization tool for material investigation. Particular attention is paid to the exploration of transient phenomena in the dynamic pseudo-MOS operation. A significant I-V hysteresis is experimentally revealed when high voltages are applied on the substrate acting as a gate. Long current relaxation (>100s) in accumulation and depletion, in darkness and under illumination, demonstrate the dominance of carrier trapping at grain boundaries over oxide charging and/or SRH generation-recombination intra-grain phenomena. The dynamic regime analysis shows remarkable data retention duration and suggest further investigations of polycrystalline silicon wires for memory applications may be useful.