Protecting quantum memories using coherent parity check codes

Abstract

Coherent parity check (CPC) codes are a new framework for the construction of quantum error correction codes that encode multiple qubits per logical block. CPC codes have a canonical structure involving successive rounds of bit and phase parity checks, supplemented by cross-checks to fix the code distance. In this paper, we provide a detailed introduction to CPC codes using conventional quantum circuit notation. We demonstrate the implementation of a CPC code on real hardware, by designing a [[4, 2, 2]] detection code for the IBM 5Q superconducting qubit device. Whilst the individual gate-error rates on the IBM device are too high to realise a fault tolerant quantum detection code, our results show that the syndrome information from a full encode–decode cycle of the [[4, 2, 2]] CPC code can be used to increase the output state fidelity by post-selection. Following this, we generalise CPC codes to other quantum technologies by showing that their structure allows them to be efficiently compiled using any experimentally realistic native two-qubit gate. We introduce a three-stage CPC design process for the construction of hardware-optimised quantum memories. As a proof-of-concept example, we apply our design process to an idealised linear seven-qubit ion trap. In the first stage of the process, we use exhaustive search methods to find a large set of [[7, 3, 3]] codes that saturate the quantum Hamming bound for seven qubits. We then optimise over the discovered set of codes to meet the hardware and layout demands of the ion trap device. We also discuss how the CPC design process will generalise to larger-scale codes and other qubit technologies.