Proposed unified 32-bit multiplier/inverter for asymmetric cryptography

Abstract

Arithmetic in GF(2n) finite fields in asymmetric cryptography is the key of an efficient cryptosystems implementation. Thus, cryptosystems based on algebraic curves such as Hyper/Elliptic curves (ECC,HECC) and Pairings need a big number of arithmetic operations. They required several GF(2n) inversions and multiplications which are the most time and area consuming operations. This paper describes a hardware architecture for computing both modular multiplication and modular inversion in GF(2n) finite fields, based on a Modified Serial Multiplication/Inversion (MSMI) algorithm. The algorithm is suitable for both hardware implementations and software implementations. The proposed design performs 8-bits, 16-bits, 32-bits or 64-bits modular multiplication or inversion. Our design was modeled using VHDL and implemented in the Xilinx FPGAs Virtex6. Implementation results prove that our MSMI uses only 219 FPGA slices, it achieves a maximum frequency of 150 MHz and it computes 163-bits modular multiplication in 4.21 µ secs.