Abstract
Routers are the most common transmission devices over the Internet. Architecture of the routers can be improved to fully utilize the chances to save energy related to the CMOS based transmission equipment. One prime approach for controlling and managing the power dissipation of the CMOS devices is Dynamic Voltage and Frequency Scaling (DVFS). This paper implements the DVFS in a CMOS device programmed as a router for studying multiple factors impeding energy saving by using Dynamic Clock Generation (DCG) and Dynamic Clock Selection (DCS). The authors emphasize on the performance evaluation of such frequency scaled CMOS devices, in which the service rate vary according to the state of an underlying finite-state, continuous-time Markov model. Furthermore, this paper establishes the relationships of critical factors (in/)directly effecting power consumption of these devices. Aforementioned factors and their dependencies such as the arrival and service rates, queuing lengths and thresholds in such systems facilitate the changing dynamics of functions and services for appropriate clock state of the device. Thus, the resulting model is quite complex to be proved analytically or numerically. We investigate and implement PROGRES to affirm the numerical models' accuracy for capturing the service rate transitions of the proposed control policies with detailed performance analysis and discussion. Furthermore, PROGRES also scales the arrival rates and queue lengths, while ensuring the controlled transition rates of the modulating Markov process in the programmable router. Two control models against single service rate for benchmarking. These techniques and numerical experiments allow us to identify and evaluate the trade-offs between energy consumption and system performance in the futuristic programmable networking devices with resulting approximations are promising at network, node and functional levels.
Highlights
In recent years innovative Internet services and applications, such as Internet of Things (IoT), Augmented Reality, Interactive Gaming, Remote Medical Surgery, Self-driving cars, Delivery Drones, Social Networking and e-commerce, etc., are experiencing a prodigious development
This paper focuses on the frequency scaling of CMOS based network devices to implement multiple service rates in a packet processing engine, which has been widely believed as one of the effective approaches to achieve the goal of reducing the power dissipation [2] in future networking equipment
When a section of logic blocks is not used for a certain function, the clock signal to the logic blocks will be disabled to decrease the power consumption of the clock network. 28% lower power consumption is reported in Xilinx Virtex-5 FPGA by using clock gating [15]
Summary
In recent years innovative Internet services and applications, such as Internet of Things (IoT), Augmented Reality, Interactive Gaming, Remote Medical Surgery, Self-driving cars, Delivery Drones, Social Networking and e-commerce, etc., are experiencing a prodigious development. This paper focuses on the frequency scaling of CMOS based network devices to implement multiple service rates in a packet processing engine, which has been widely believed as one of the effective approaches to achieve the goal of reducing the power dissipation [2] in future networking equipment. We research and identify that the hardware working frequency transition rate is proportional to the device power consumption, which can be considered as the true counterpart of the classical energy efficiency. 2) We investigate the dependent factors and their impact on controlling the hardware frequency transition rates In this type of study, we show that an appropriately scaled queuing size, packet arrival rate, service rate, threshold step size can converge to normalization.
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