Programming Strategy Optimization of RRAM Fabricated by 28 nm Standard CMOS Process

Abstract

The switching characteristics of HfOx-based resistive switching random access memory (RRAM) fabricated on front-end of 28 nm standard CMOS process are investigated. The integration of RRAM in the front-end of the CMOS process would minimize the influence of parasitic parameters caused by interconnection line and interlayer oxide on the one transistor one RRAM (1T1R) cells. By adopting pulse program-verify measurement for cycling test, we observe two nonideal phenomena in the commercialized RRAM devices for the first time: 1) low resistance state (LRS) current periodically decays exponentially accompanied by incremental SET pulse number and then increases abruptly when the cycle reaches a certain level and 2) high resistance state (HRS) current fluctuated dramatically during RESET operation. The current fluctuation is mainly due to the generation of new oxygen vacancies (Vos) near the bottom electrode and gap region by electrons trapping/detrapping. By adopting efficient pulse amplitude modulation, the optimized programming strategy has greatly reduced the switching instability and improved the endurance of the devices. Mechanisms of the instability and the optimization strategy are explained by a modified trap-assisted tunneling (TAT) model based on the generation and redistribution of Vos during cycling operations.