Abstract
The authors propose a parallel and programmable VLC (variable length code) decoder which includes the arithmetic representation of codewords and codeword regularity. They also propose its hardware configuration. With this hardware configuration, the parallel VLC decoder is faster and has less memory than the traditional decoder. With this approach, RLC (run length coding) and the VLC can be efficiently decoded. Since the hardware configuration works with reloadable RAM tables, the proposed algorithm can be operated as a programmable RLC and VLC decoder. In addition, an extended parallel VLC decoding algorithm which can decode two codewords in a single clock cycle is also provided. The proposed fast and programmable variable length decoder is suitable for future compression video systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Published Version
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