Abstract
In this era where the growth of computer performance is significantly flattening, new parallel computer architectures are needed to continue to fuel that growth. One candidate architecture to fuel this growth is a recently proposed dataflow processor that is meant to be tiled together into a fabric to create a polymorphic computer (i.e. a reconfigurable computer whose architecture can be changed to match the software) where program instructions can be independently migrated in a fine-grained manner around the fabric to logically change the computer architecture. This work provides a summary of the dataflow processor’s instruction set and details how to write programs for this processor. The techniques that are presented to write programs for this processor are diagramming and 12 building block programming patterns. The 12 patterns are: Operations with a Constant, Simple Copy, Pitch (Discard), Counters, Critical Sections, Funnels (Gathers), Distribution Tree (Scatters), Lookup Tables, Single Value Selection, Single Value Steering, Switch (Multi-Value Steering), and Loops. These patterns are expected to benefit future compilers. In addition, the ideal timing results of several test algorithms that are implemented in this processor and that utilize the above patterns are presented. • Background summary of a polymorphic computing dataflow processor’s instruction set • Program diagramming methods for a polymorphic computing dataflow processor • 12 Programming patterns in a polymorphic computing dataflow processor • Ideal timing results of several test algorithms in polymorphic computing fabric
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