Abstract
PASTTREC is an 8-channel readout Application-Specific Integrated Circuit (ASIC) designed for the Straw Tracking System (STS) in the HADES experiment and for the Straw Tube Tracker (STT) and the Forward Tracker (FT) detectors in the PANDA experiment, both at the FAIR facility. Since more than 5000 ASICs were produced for both experiments, efficient qualification tests are required. For this purpose, the multi-chip test setup and dedicated verification procedures were developed. In this paper, the measurement results for the first batch of 140 Front-End Boards (FEBs), each hosting two ASICs, are presented. Since a significant number (280) of PASTTREC chips were tested, obtained statistical distributions of key parameters are also reported. The estimated yield (97%) and the process-related spread of the chip parameters are discussed.
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