Process Window, and Process Optimization in Both Low and High Na EUV Processes for Advanced Logic Technologies Nodes

Abstract

As we know, if we consider Extreme Ultra-Violet (EUV) stochastics induced defectivity, the minimum pitch for the line/space is around 36~ 40 nm and 48 ~ 50 nm for the contact holes and vias in 0.33 NA EUV lithography. From the current roadmap, the ultimate minimum pitch of the metal layer in EUV lithography is 14 nm, which will be realized by double patterning with high NA EUV tool. After some studies, we believe that the optimum pitch for the line/space is believed to be around 28 nm and 38 ~ 40 nm for the contact holes and vias with 0.55 NA EUV lithography. We have done a simulation study for some typical patterns with the anchoring metal pitch of 28 nm in high NA EUV lithography with self-developed program. Generally speaking, critical structures in advanced logic technologies nodes are Tip-to- Tip structures, the minimum area structures, etc. For these patterns, we have briefly studied the influence of Source Optimization (SO) on and the impact from coma Y to the process window and we have found that the contribution of SO is not significant (<5%) and we have determined the specification on the optical aberration based on our understanding in the requirement from process window. Due to the high kl nature of EUV lithography, we have also done a study on a 45° local interconnect pattern in a 3 nm CFET SRAM with both low NA and high NA EUV processes.