Process Variation Aware Design of Multi-Valued Spintronic Memristor-Based Memory Arrays

Abstract

The missing fourth passive element, predicted by L. Chua and denoted by memristor, has recently been in the research focus since its titanium dioxide thin film realization is reported by HP. Following that, the spintronic memristor, which is based on the magnetic tunneling junction, is presented as an alternative to the thin film memristor. The nano-scale geometry size of the memristor makes it hard to control its dimensions due to the process variation resulting from the fabrication process. This process variation results in yield degradation in the spintronic memristor-based memory arrays. This yield degradation is more significant when the spintronic memristor is utilized as a multi-valued memory elements. In this paper, the impact of the process variation on the spintronic memristor-based memory yield is discussed for the 1-bit, 2-bit, and ${n}$ -bit memory element. Moreover, two approaches are introduced to enhance the memory yield.