LRT links Multibus into Ethernet

Abstract

Memristor, the missing fourth element predicted by L. Chua, has recently been in the research focus since HP Lab reported the first TiO2 thin film memristor realization. The nano-scale geometry size of the memristor makes it difficult to control its dimensions due to the process variation incurred in the fabrication process. This process variation results in yield degradation in the memristor-based memories. This yield degradation is more severe when the memristor device is used as a multi-valued memory element. In this paper, the impact of the process variation on the memristor-based memory yield is investigated for the 1-bit, 2-bit, and n-bit memristor memory element. In addition, two approaches are proposed to improve the memory yield. Therefore, the main objective of this work is to introduce a statistical yield simulation flow to calculate the memory statistical yield under process variations and investigate the effect of different design knobs on this statistical yield regardless of the memristor models and the process variation models used. Simulation results reveal that for 1-bit memristor-based memories, the nominal write voltage should be increased by 30% and the nominal threshold value (i.e., the midway memristance value between the memristor ON resistance and the memristor OFF resistance) should be increased by 65% to achieve the maximum yield. Finally, the paper lists the minimum memristor size that should be used to achieve a 99.9% memory yield for n-bit memories. These results show how the process variation imposes limitations on the minimum memristor device size when multi-valued memories are to be designed.