Abstract
Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.
Highlights
Scaled transistors are affected by three kinds of process variations
A diversity of systematic process variations is caused by non-idealities of process equipment, like inhomogeneity of gas flow or temperature distributions, or imperfect control of parameters like the distance between the last lens and the wafer in lithography, the so-called defocus
This paper reports about results obtained in the cooperative project SUPERAID7 [2], funded within the Horizon 2020 programme of the European Union, and partly about related background within the Horizon 2020 programme of the European Union, and partly about related background work from Fraunhofer IISB, and from partners as cited
Summary
Scaled transistors are affected by three kinds of process variations. Most frequently and since long discussed in the literature are statistical process variations which are caused by the granularity of matter, such as Random Dopant Fluctuations (RDF). For aggressively scaled three-dimensional devices such as FinFETs or nanowires as shown, systematic variations of simple geometrical parameters such as the gate length must be considered, and three-dimensional shapes may vary, critically affecting device performance. For aggressively scaled three-dimensional devices such as FinFETs or nanowires as shown in Figure 1, systematic variations of simple geometrical parameters such as the gate length must be considered, and three-dimensional shapes may vary, critically affecting device performance.
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