DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Abstract

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles.