Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

Z.A Noor Faizah,Y Siti Munirah,P.J Ker,R Mohd Firdaus,Ibrahim Ahmad,P S Menon,E Md Fazle,S Sharif,S.Z Abd Rahim,S.A Zainol Murad,M.M Ramli,M.M.A.B Abdullah,S.S Mat Isa,N Mat Saad,M.F Ghazali

doi:10.1051/matecconf/20167801017

Abstract

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO 2 ) as dielectric and Tungsten Silicide (WSi 2 ) and Titanium Silicide (TiSi 2 ) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where V TH and I OFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

Highlights

The gate length of MOSFET has continually been scaled down through last few decades to create smaller and smaller device in order to fabricate high density chips
Taguchi method was applied in this research to optimize the threshold voltage (VTH) and leakage current (IOFF)
By following the L9 Orthogonal Array template, all four control factors are varied using the dopant values for which produced the output near to the ITRS 2013 prediction

Summary

Introduction

The gate length of MOSFET has continually been scaled down through last few decades to create smaller and smaller device in order to fabricate high density chips. As MOSFET is scaled down it provides various kind of technical challenges and this become worsen when it comes to the nano-meter dimensions. This is because of the problems such as Short Channel Effects (SCE), increased leakage current, and lack of pinch off [1]. These modules are important in designing and optimizing the process parameter [2] of a semiconductor device.

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Results

Conclusion