Process Optimization for 3-D IC Assembly

Abstract

The challenge for three-dimensional integrated circuit assembly is how to manage warpage and thin wafer handling to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have microbumped die with pitches ranging from 120 μm down to 60 μm. The high density of pads and the large die size make it extremely challenging to ensure that all of the microbump interconnects are attached to a thin Si interposer (ITP). In addition, the low standoff between the die and ITP makes it difficult to underfill. A likely approach is to first attach the die to the ITP and then the die/ITP subassembly to the substrate. In this scenario, the die/ITP subassembly is comparable to a monolithic Si die that can be flip chip attached to the substrate. In this article, we discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do two-and-half-dimensional assembly in an outsourced assembly and test facility.