Cost Modeling and Analysis for Interposer-Based 3D ICs with 3D Memory Repair Schemes

Abstract

Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for interposer-based 3D IC with 3D memory repair schemes, including the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking. The cost model contains the manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 99.2% and the pre-bond interposer test yield is lower than 99%. The Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. The total costs of three types of 3D memory repair schemes are compared. The result shows that, among three different 3D memory repair schemes, the macro level redundancy with over 20 redundancy dies has the lowest cost. For different applications, the proposed model evaluates the execution criterion or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.