Process investigations for a 30-GHz f/sub T/ submicrometer double poly-Si bipolar technology

Abstract

Major process issues are investigated to establish a manufacturable process for a 30-GHz f/sub T/ deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000/spl deg/C in order to maintain an acceptable integrity of TiSi/sub 2/ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975/spl deg/C and 1000/spl deg/C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>