Process integration issues for a 0.25 μm n‐channel metal‐oxide‐semiconductor technology

Abstract

Process integration issues for the gate structure and channel region of the enhancement mode device within a fully self‐aligned 0.25 μm NMOS technology are discussed. The optimized process gives a polysilicon (poly) gate electrode with a resistivity of 0.02 Ω‐cm, a midgap interface trap density of 2×1011 eV−1 cm−2, and a catastrophic breakdown field greater than 10 MV/cm for the 11.5 nm gate oxide. The annealing conditions that provide an n+ poly gate with the correct work function and low resistivity compatible with a thin gate oxide are described. Shallow channel implant broadening effects on device characteristics have been studied with simulations and fabricated devices.