Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Hsiang-Hung Chang,Pei-Jer Tzeng,Chun-Hsien Chien,Tzu-Kun Ku,Cheng-Ta Ko,Ding-Ming Kwai,Ting-Sheng Chen,Yu-Wei Huang,Chia-Hsin Lee,Cha-Hsin Lin,Yu-Chen Hsin,Jen-Chun Wang,Ming-Jer Kao,Yung-Fa Chou,Zhi-Cheng Hsiao,Chau-Jie Zhan,Wei-Chung Lo,Chung-Chih Wang

doi:10.1109/vlsi-tsa.2015.7117587

Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Hsiang-Hung Chang, Pei-Jer Tzeng + Show 16 more

https://doi.org/10.1109/vlsi-tsa.2015.7117587

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Publication Date: Apr 1, 2015

Citations: 1

Affiliation: ITRI International, Industrial Technology Research Institute

#Backside Illuminated CMOS Image Sensor #3DIC Technology + Show 8 more

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Abstract

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

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