Three-tier chips stack with TSVs for backside illuminated image sensor/ADC/ISP

Abstract

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to less than 5 μm for light detection from the backside. After thinning process, the backside is permanently bonded to a 500μm-thick glass carrier substrate with a transparent thermal set bonding material. After thinning, the total thickness variation of 1μm is obtained because the thermal plastic material flow during bonding process resulted in excellent thickness uniformity. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. In the assembly process of CMOS image sensor stack, firstly the analog-to-digital conversion chip was stacked onto the image signal processor chip by thermal compression bonding. Optimized bonding conditions of 250 °C/5 sec under the bonding force of 13N were chosen and determined. Subsequently, after the stack of analog-to-digital conversion chip onto the image signal processor chip, the CMOS image sensor chip was bonded onto the image signal processor/analog-to-digital conversion stack. To connect all the solder bumps between CMOS image sensor and analog-to-digital conversion chip, the higher bonding force of 18N was selected. Joined-well solder joints between these two chips could be achieved. Finally, the stacked CMOS image sensor module was attached to a print circuit board by adhesive material and wire bonding was conducted to finish the electrical connectivity between CMOS image sensor stack and print circuit board.