Process Feasibility and Reliability Performance of Fine Pitch Si Bare Chip Embedded in Through Cavity of Substrate Core

Abstract

We demonstrate the concept and fabrication of through cavity core device-embedded substrate for fine-pitch Si bare chips with pad pitches down to 60 $\mu \text{m}$ . Instead of using a real active Si chip, we embedded a Si test element group inside a through cavity of the core. To adjust to the thickness of the passive device with a maximum thickness of 150 $\mu \text{m}$ , the Si chip was thinned to 120 $\mu \text{m}$ , not including bump height. After placing a chip, the cavity is filled by laminating a two-layer structure Ajinomoto build-up film from both sides of the substrate core. To accurately place the chip in the cavity, we strictly controlled the lamination conditions and curing temperature of the epoxy resin. Laser via drilling produced the best alignment for fine-pitch small pads using the local alignment marks of each test frame kit with overhead epoxy resin of the Cu mark pattern removed. To produce a high-quality microvia interconnection to the Al pad of the Si chip, we used a new, combined desmearing technique that included a plasma treatment with CF4 + O2 mixed gas. Finally, we discussed the production yield and reliability of the fine-pitch Si bare chip-embedded substrate using the daisy-chain structure consisted of Si chip pattern, microvia on Si pad, and substrate tracks.