Process dependency on threshold voltage of GaN MOSFET on AlGaN/GaN heterostructure

Abstract

GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) with recessed gate on AlGaN/GaN heterostructure are reported in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. Negative threshold voltages were commonly observed in all devices. To investigate the reasons of the negative threshold voltages, different oxide thickness, etching gas and bias power of inductively-coupled plasma (ICP) system were utilized in the fabrication process of the GaN MOSFETs. It is found that positive charges of around 1×1012q/cm2 exist near the interface at the just threshold condition in both silane- and tetraethylorthosilicate (TEOS)-based devices. It is also found that the threshold voltages do not obviously change with the different etching gas (SiCl4, BCl3 and two-step etching of SiCl4/Cl2) at the same ICP bias power level (20–25W) and will become deeper when higher bias power is used in the dry recess process which may be related to the much serious ion bombardment damage. Furthermore, X-ray photoelectron spectroscopy (XPS) experiments were done to investigate the surface conditions. It is found that N 1s peaks become lower with higher bias power of the dry etching process. Also, silicon contamination was found and could be removed by HNO3/HF solution. It indicates that the nitrogen vacancies are mainly responsible for the negative threshold voltages rather than the silicon contamination. It demonstrates that optimization of the ICP recess conditions and improvement of the surface condition are still necessary to realize enhancement-mode GaN MOSFETs on AlGaN/GaN heterostructure.