Process control of contact holes for sub-half-micron CMOS technology

Abstract

Difficulties in controlling size of contact holes in a sub-half-micron CMOS process using planarisation by resist etch back are discussed. In particular, the limitations of using top anti-reflective coatings to overcome thin film effects on transparent substrates are calculated by simulation. Use of bottom anti-reflective coatings to improve uniformity are described through practical results.