Abstract
Control of contact hole sizes in a sub-half-micron CMOS process using planarisation by resist etch back and chemical mechanical polishing is discussed. The limitations of using top anti-reflective coatings to overcome thin film effects on transparent substrates are calculated by simulation. Use of bottom anti-reflective coatings to improve uniformity in the resist etch back process are described through practical results which additionally show that comparable results are achieved in the chemical mechanical polishing process but in the absence of a bottom anti-reflective coating.
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