Abstract
This paper presents an inclusive study and analysis of graphene-based MOSFET device at 32nm gate length. The analysis was based on top-gated structure which utilized Hafnium Dioxide (HfO 2 ) dielectrics and metal gate. The same conventional process flows of a transistor were applied except the deposition of bilayer graphene as a channel. The analytical expression of the channel potential includes all relevant physics of bilayer graphene and by assuming that this device displays an ideal ohmic contact and functioned at a ballistic transport. Based on the designed transistor, the on-state current (I ON ) for both GNMOS and GPMOS shows a promising performance where the value is 982.857uA/um and 99.501uA/um respectively. The devices also possess a very small leakage current (I OFF ) of 0.289578nA/um for GNMOS and 0.130034nA/um for GPMOS as compared to the conventional SiO 2/ Poly-Si and high-k metal gate transistors. However, the devices suffer an inappropriate subthreshold swing (SS) and high value of drain induced barrier lowering (DIBL).
Highlights
The never ending process challenge of scaling down to cramming more transistor in a single chip which was coined by Gordon E
A 32nm gate length of NMOS and PMOS bilayer graphene-based transistor were virtually design and tested for its functionality where the performance parameters were set to be in line with the International Technology Roadmap of Semiconductor, ITRS 2011 prediction for which the threshold voltage (VTH) is 0.103 ± 12.7% V, on-state current (ION) greater than 100nA/um and leakage current (IOFF) lower than 150nA/um
The performance of the transistors was measured in terms of threshold voltage (VTH), leakage current (IOFF), and on-state current (ION) which was specified in International Technology Roadmap of Semiconductor (ITRS) 2011
Summary
The never ending process challenge of scaling down to cramming more transistor in a single chip which was coined by Gordon E. Moore has led to an invention of new device design and proposed materials. Problems such as transport degradation, the increasing of parasitic effect and aggravated on-off transition attributed from the miniaturization of the channel length. The carbon-based material is proposed as an alternative to SiO2 and now is rising in nanoelectronic design due to low cost of manufacturing and its outstanding properties such as extremely high mobility together with a promising ability to be scaled down to a smaller gate length. A 32nm gate length of NMOS and PMOS bilayer graphene-based transistor were virtually design and tested for its functionality where the performance parameters were set to be in line with the International Technology Roadmap of Semiconductor, ITRS 2011 prediction for which the threshold voltage (VTH) is 0.103 ± 12.7% V, on-state current (ION) greater than 100nA/um and leakage current (IOFF) lower than 150nA/um. The simulation tools of ATHENA and ATLAS in Silvaco TCAD Tools was utilized during the simulation process
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
