Abstract
This work demonstrates a methodology for evaluating the multiple feature error budget of NAND-Flash Gate layer and investigates the process capability of the Double Patterning Technology (DPT) options, LELE and Spacer, for NAND Flash 32nm and below. Since the effective k1 limit for DPT is near 0.14 for dense 1D features, three types of ASML scanners are potential candidates for imaging such devices: XT:1400, XT:1700i and XT:1900i. We will present the results of a simulation evaluation of the DPT process capability of these scanners for NAND-Flash Gate layer with 32nm and 22nm half pitch. The DPT capability involves not only lithography but also the subsequent patterning steps of the selected process flow. Moreover, the pattern sensitivity to scanner parameter variations increases with further scaling. It is therefore crucial to take into account the reasonable budgets of scanner dose, focus and overlay errors as well as the error budgets of film deposition, etch and mask registration. This work will not only evaluate the LELE DPT and Spacer feasibility for the mentioned scanners but also analyze the main contributors of CDU in DPT processes and indicate directions we may follow to improve.
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