Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

Abstract

Welcome to the 14th ACM/IEEE International Symposium on Low Power Electronics and Design! The 2009 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to San Francisco, the liberal fog-city of million rainbows by the bay in California, USA. On a par with this great location, a strong and diverse technical program features four exciting keynote talks from leaders in the field, two plenary special sessions in line with our symposium theme on Green Data Centers and Computing, a technical panel on SoC Power management, and four informative half-day embedded tutorials scheduled for the last day of the symposium. New for this year's ISLPED has been identified as the symposium theme with an array of invited keynote speeches, special sessions and tutorials covering this theme. Dr. Percy Gilbert, VP of Technology Development at IBM, will give a keynote on advances in process technology and IBM collaborative ecosystem for leadership power performance SOC designs on Wednesday. The Thursday keynote will be delivered by Dr. Kevin Zhang, director of advanced design and Intel Fellow, who will discuss the opportunities and challenges of circuit design in Nano-Scale CMOS era. We will have two keynote speeches on Friday by Dr. Mojy Chian, the senior VP of the newly formed Global Foundries and by Dr. Yankin Tanurhan, VP of engineering and design at VirageLogic. Dr. Mojy Chian and Dr. Yankin Tanurhan will give talks on the challenges of low-power design enablement for foundry technology offerings and various opportunities in the semiconductor industry for the IP suppliers. These keynotes talks cover the topic from foundry technology to IP design and will be interesting to see the speakers' perspectives on what are the demands of IP design from advanced technologies. New for ISLPED 2009 is the introduction of a theme. This year's theme focuses on green computing toward which special sessions and tutorials are lined up. On Wednesday, we have a two-hour special session on data centers including data centers power management, integrated compute and packaging solutions, and more by Prof. Massoud Pedram, University of Southern California, Prof. Tom Wenisch, University of Michigan, Cullen Bash, principal scientist and research manager at Hewlett Packard Labs, and John Carter, manager of power-aware systems at IBM Austin Research Laboratory. The Thursday special session welcomes three speakers, Dr. Kiyoo Itoh, fellow of Hitach, Al Fazio, fellow and director of Memory Technology Development at Intel, and Prof. Suman Datta form Pennsylvania State University covering topics including low power and future non-volatile memories, low voltage circuits and transistors. On Thursday, a panel is scheduled on SoC Power Management and its controversial topics. This panel will be moderated by Brian Fuller who is an editor and consultant. We have four panelists including Sandeep Mirchandani from Broadcom, Sanjeev Das from NXP, Ran Avinun from Cadence, and Camille Kokozaki of IDT. The four embedded tutorials on Friday are organized around major themes of (1) semiconductor technologies for computing, and (2) system design issues with emerging technologies. Prof. Kaushik Roy of Purdue University will introduce ultra low voltage CMOS. Prof. Suman Datta of Pennsylvania State University and Prof. Vijay Narayanan of Pennsylvania State University will cover transistors to architectures. Prof. Vijay Raghunathan of Purdue University will introduce the topic of self-powered embedded systems and Dr. Norm Jouppi, fellow of HP Labs and Prof. Yuan Xie of Pennsylvania State University will discuss emerging technologies and their impact on system design. We have a very exciting technical program in ISLPED 2009. Out of 208 paper submissions that we received, 72 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 25% for regular and short papers (52 papers), or 35% including the additional 20 posters. Topics range from low power technology, circuits, and memory; low voltage analog and RF design; power aware design and tools; power efficient architecture techniques; and system and application level power optimization. The program is organized into eleven technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as one interactive poster session that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition ISLPED includes industry sessions and exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. Winning entries to the annual Student Low Power Design Contest will also be featured in a separate technical session in ISLPED.