Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

Abstract

On behalf of the organizing committee for the 2012 ACM International Symposium on Physical Design (ISPD), we welcome you with great pleasure to Napa Valley, California, for the symposium. Continuing the fine tradition established by its twenty predecessors, a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and fifteen editions of ISPD in the current form since 1997, the 2012 ISPD provides a premier forum to exchange ideas and promote research on critical areas related to the physical design of VLSI systems and other related systems. We received over 60 submissions from all around the world. After a rigorous, month-long, double-blind review process, the Technical Program Committee (TPC) met to select papers to be included in the technical program based on over 290 reviews provided by 21 TPC members and 41 external reviewers. Only 20 papers were selected to be presented in this symposium. These papers present advances in floorplanning, placement, and routing, address challenges in advanced processes, identify opportunities in emerging technologies, offer new cooling and clocking solutions, and propose novel gate sizing techniques. In addition, the program is complemented by one keynote speech and twelve invited talks delivered by distinguished researchers in both industry and academia. Dr. Burn Lin from TSMC, a member of the United States National Academy of Engineering, will present in the keynote speech candidate solutions to push lithography beyond the 20nm node. A commemorative session on Monday afternoon allows us to pay tributes to Professor Chung-Laung (Dave) Liu, an outstanding teacher, a pioneer in EDA, and a Phil Kaufman Award recipient. His former students will share with us how Professor Liu's research transformed ad hoc EDA to algorithmic EDA and the far reaching impacts of his work, as illustrated in today's nanometer-era routing solutions and the wide-spread use of simulated annealing in EDA. Professor Liu will also grace the symposium with a delightful recount of his 30 years in EDA. An invited session on Wednesday morning will focus on research topics related to congestion-driven logic and physical synthesis. Other invited talks will be interspersed with the presentations of accepted papers, covering the following topics: design-aware lithography, challenges in the 3D integration of CMOS-memristors, synthesis of minimal functional skew clock trees, and analysis of power grids. An invited talk will showcase the latest edition of the ISPD contest. Since 2005, ISPD has organized highly competitive contests to promote and advance research in placement, global routing, and clock network synthesis. This year, we feature a new contest topic, namely, discrete gate sizing. This year's contest continues to attract a large number of participants from all over the world. The results of this contest will be announced by the ISPD Contest Chair. Continuing with the tradition of the past contests, a new large-scale real-world benchmark suite for gate sizing will also be released.