Abstract

Self-timed (speed-independent) devices are often considered highly reliable. However, up until now the issues of the development of fault-tolerant self-timed digital circuits have been poorly studied. By adapting existing methods of the fault-tolerant combinational circuit design for self-timed implementation, a number of technical solutions and methods are proposed that make it possible to significantly increase the reliability of key elements, such as indicators of transition process completion. It is shown that traditional methods of improving the reliability of self-timed devices do not make it possible to achieve the parameters expected by the developers of digital devices. Therefore, one of the key challenges in the creation of faulttolerant self-timed circuits is the development of original methods of the improvement of reliability and faulttolerant design. It leads to the problem of self-timed analysis of developed fault-tolerant solutions. The relationship between energy consumption scaling and reliability is analyzed. An indicator of energy reliability is proposed that makes it possible to compare digital circuits using three key indicators (power consumption, reliability, and performance).

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call