Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement

Abstract

A new methodology of probabilistic analysis of CMOS physical defects in complex gates for the defect-based test is proposed. It is based on the developed approach for the identification and estimation of the probability of actual faulty functions resulting from shorts caused by spot defects in conductive layers of IC layout. The aim of this methodology is realistic representation of physical defects in fault models. The list of defects, identified faulty functions, defect coverage table, conditional defect probabilities, and effectiveness and optimal sequence of test patterns are the main output data of probabilistic-based faults characterisation. The description of such characterisation and experimental data obtained for industrial standard cell library in 0.8 μm CMOS technology are presented. Special software tool named FIESTA has been developed for the automation of the probabilistic-based fault characterisation. The main destination of this tool is the investigation of gates from Cadence standard cell library. The experimental data obtained during complex gates characterisation are used for the estimation of the physical defects coverage by hierarchical defect simulation. At the higher level simulation the developed functional fault model was used, at the lower level we used the defect/fault relationships in the form of the defect coverage table and the conditional defect probabilities. Analysis of the quality of 100% stuck-at fault (SAF) sets in relation to physical CMOS defects in complex gates was performed. The investigation of the correlation between the fault coverages for SAFs and defects of short type for two benchmark circuits was done as well.