CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing

R.R Fritzemeier,J.M Soden,C.F Hawkins

doi:10.1109/cicc.1991.164091

CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing

R.R Fritzemeier, J.M Soden + Show 1 more

Open Access

https://doi.org/10.1109/cicc.1991.164091

Copy DOI

Publication Date: May 12, 1991

Citations: 10

Affiliation: Sandia National Laboratories, University of New Mexico

#CMOS Integrated Circuit #Stuck-at Fault + Show 8 more

Abstract
Full-Text
Similar Papers

Abstract

The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I/sub DDQ/ testing, is presented. >

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Similar Papers

Paper Title

Journal

Date

Author

View more papers

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.