Abstract
A prescaler using complementary clocking dynamic flip-flops (CCD-FF) is presented and implemented in a synthesiser using 0.18 µm CMOS technology. The maximum operating frequency of the proposed CCD-FF is up to about 10 GHz and the prescaler using this flip-flop operates up to 5.1 GHz. The proposed CCD-FF has not only a high operating frequency but also low power consumption since it is based on the scheme of the conventional true single phase clocking (TSPC) flip-flop with no static DC current. The RMS current consumption of designed 16/17 dual-modulus prescaler is only 1.39 mA at 4 GHz.
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