Abstract
This paper deals with development and irradiation test of a dynamic memory scrubbing routine for the CPU-coupled, SRAM-based memory of the commercial off-the-shelf (COTS) TMS570LS3137 microcontroller. The techniques combine hardware/software co-design concepts, resulting in low design complexity, high performance and high reliability at the same time. The algorithm uses the CPU-coupled ECC Error Correction Code (ECC) mechanism to correct Single Bit Upsets (SBU). It has been developed with the objective of using the COTS microcontroller with dual-CPUs in lockstep as part of a particle accelerator Detector Control System (DCS). The major objective of this paper is to present the on-chip dynamic memory scrubbing mechanism, which prevents SBU error accumulation in the SRAM cells, and provide irradiation test results to proof correct functioning. The current implementation successfully corrects SBUs with a mean time of 5.5 milliseconds as concluded from the tests.
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