Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs

Abstract

FPGAs are the most prominent electronic devices used in space, military, and commercial applications. This is because of the reprogrammable feature in FPGAs. The electronic and computational components are sensitive to various types of events caused by ionisation effects. The problem at hand is effectively addressed by a fault-tolerant method known as Triple Modular Redundancy (TMR). Triple Modular Redundancy (TMR) has been demonstrated as an effective and dependable technique for mitigating the impacts of single-event upsets (SEUs) and single-event transients (SETs). However, to ensure effective mitigation of SETs, an additional delay element is required. However, the implementation of a TMR system may incur higher costs due to the requirement for additional hardware resources. Subsequently, numerous studies have focused on conventional fault-tolerant techniques with the aim of reducing the hardware overhead associated with TMR, although these efforts have not yielded satisfactory results. In order to tackle this issue more effectively, this paper introduces a novel error analysis approach. This approach works based on the error percentage algorithm and also proposes the other method, a preferential method for reducing the overhead of the hardware in existing fault-tolerant techniques. The proposed work is applied to the multiplier circuit to analyse its efficiency. The proposed work reduces the hardware resources by 48% when compared with the existing work.