Predictive SAR ADC with two-step loading technology for energy reduction

Abstract

This paper presents a novel two-step loading technology to cut down the analog-to-digital converter (ADC) loading phase energy consumption when prediction algorithms is employed in quantization. By loading initial guess code’s logical 1 and logical 0 in the sequence of time, proposed technology can qualitatively reduce the charge variation between capacitors’ top- and bottom-plate. Consequently, the energy produced by loading phase is partly saved. Also, to verify the proposed method, a 12-bit Vcm-based predictive successive approximation register (SAR) ADC predicting higher 7 bits is designed in 0.13 μm CMOS process with a 0.6 V supply. Given a full-scale ECG signal, the ADC achieves 24.76% loading phase energy reduction in average. Given a 10 Hz full-scale sinusoid signal and a slope signal, the ADC saves 24.5% and 24.45% loading phase energy in average, respectively. Further, given a 41.5 Hz full-scale sinusoid signal, the proposed ADC exhibits 11.76 effective number of bit (ENOB) and 86.5 dB spur-free dynamic range (SFDR) at 10k Hz sample rate.