Abstract

Due to inherent planarization effects when coating on topography, both the resist and organic bottom anti reflective coating (BARC) thicknesses vary, as do the final reflectivity and critical dimensions (CD). As a consequence, determination of the optimal BARC thicknesses and prediction of the lithographic performance, taking into account topography effects over the whole chip, are not easy. Lithographic performances are thus usually measured or calculated using modeling over plane wafers. In this paper, we propose a practical representation of the lithographic performance of the BARC/resist bilayer and a simulation algorithm allowing determination of both the optimal BARC thicknesses and the lithographic performance window over the whole chip. Practical examples are given demonstrating the role of such a simulation.

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