Predicting the usefulness of a block result: a micro-architectural technique for high-performance low-power processors

Abstract

This paper proposes a micro-architectural technique in which a prediction is made for some power-hungry units of a processor. The prediction consists of whether the result of a particular unit or block of logic will be useful in order to execute the current instruction. If it is predicted useless, then that block is disabled. It would be ideal if the predictions were totally accurate, thus not decreasing the instruction-per-cycle (IPC) performance metric. However, this is not the case: the IPC might be degraded which in turn may offset the power savings obtained with the predictors due to the extra cycles to complete the execution of the application being run on the processor. In general, some logic map determine which of the block(s) that have a predictor associated will be disabled based on the outcome of the predictors and possibly some other signals from the processor. The overall processor power consumption reduction is a function of how accurate the predictors are, what percentage of the total processor power consumption corresponds to the blocks being predicted, and how sensitive to the IPC the different blocks are. A case example is presented where two blocks are predicted for low power: the on-chip L2 cache for instruction fetches, and the Branch Target Buffer. The IPC vs power-consumption design space is explored for a particular micro-processor architecture. Both the average and the peak power consumption are targeted. Although the power analysis is beyond the scope of this paper, high-level estimations are done to show that it is plausible that the ideas described might produce a significant reduction in useless block accesses. Clearly, this reduction may be exploited to reduce the power consumption demands of high-performance processors.