A Low Power Branch Prediction for Deep Learning on RISC-V Processor

Abstract

A key factor in reducing power consumption for processors is to improve the accuracy of branch prediction and the optimal use of Branch Target Buffer (BTB) size. The power consumption can be reduced by improving the accuracy of branch prediction if additional increase in power consumption due to prediction logic cannot offset the gain from accurate branch prediction. For applications like Convolutional Neural Networks(CNN), we design a new method called PC-Mix to optimize branch direction prediction and BTB size for reduction of power consumption of RISC-V processors. In simulation, 2.5GHz RISC-V processor design is shown that PC-Mix reduces the power consumption of the original processor on CNN by 35% while keeping performance unchanged or better. Compared with the well-known Gshare mechanism, PC-Mix reduces the total power consumption of CNN by 4% in a worst case scenario. At the same the branch prediction accuracy of our scheme exceeds 95%. Meantime hardware overhead are reduced in the design without affecting performance.