Precise Control of Spike Anneal Process for Advanced CMOS

Abstract

Aggressive scaling of planar bulk CMOS device has resulted in the need for ultra-shallow junctions (USJ) formation. This represents some special concern are not only integration solution, but also the individual process precise control to meet the evolutional requirements. In the USJ particular, as junction thickness (depth) decreases, the series resistance of the junction increases. Therefore, the dopants concentration must to be increased to improve the resistance. Dilemma, the diffusion is an important issue in shallow junction technology. The spike anneal process was widely adopted at advanced CMOS fabrication to meet the device requirements. In this paper, how to precisely control the processes of spike anneal is discussed. The two major interacted process factors, peak-temperature and residence-time must be separately tunable, not only to meet the requirements of device parameter, but also to achieve an operational precise controlling for process setup, optimization and maintenance.