Prebond through silicon vias test based on time-to-digital conversion}{Prebond through silicon vias test based on time-to-digital conversion

Abstract

Defects in through silicon vias (TSV) not only lead to the variation of the propagation delay but also to that of the transition delay, which is more sensitive to TSV faults. A non-invasive approach for pre-bond TSV tests based on time-to-digital conversion is proposed to detect resistive open and leakage faults with picosecond accuracy. The TSVs are used as capacitive loads of their driving gates. The pulse visiting the cyclic shrinkage cells will then shrink until it vanishes completely. The shrinkage amount is digitized and compared with the expected fault-free value. The fault detection experiments are carried out with HSPICE simulations using realistic 45-nm CMOS technology models. The results show the effectiveness in the detection of resistive open defects 0.2 K$\Omega$ above and equivalent leakage resistance less than 40 M$\Omega$. . This scheme is capable of TSV quality binning; the frequencies of the input pulse or test clock have no strict limit. The estimated area overhead of the design for testability is negligible for realistic dies.