Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC)

Abstract

The through silicon via (TSV) is used for the vertical interconnection between multiple stacked layers of 3D-IC. It's an alternative to the wire bonding, which was used in planar 2D-IC. TSVs are fabricated through the Silicon substrate. TSV based 3D-IC is getting popular because of low power consumption, remapping and high density. All these benefits may be ruined because of TSV failure. In this paper, maximum possible TSV failure scenarios including (i) misalignment of TSV, Bump, Pad, (ii) fabrication defects, (iii) material impurities, (iv) short circuit path between TSV and the substrate have been illustrated, and analyzed by the delay variation. Cadence SPECTRE is used for the circuit simulation.