Pre-Silicon FEC Decoding Verification on SoC FPGAs

Victor Fernandez,Pablo Sanchez,Inigo Ugarte,Angel Alvarez,Carlos Abad

doi:10.1109/lcomm.2020.3025223

Victor Fernandez, Pablo Sanchez + Show 3 more

Open Access

https://doi.org/10.1109/lcomm.2020.3025223

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Journal: IEEE Communications Letters	Publication Date: Sep 23, 2020
Citations: 7	License type: other-oa

Affiliation: Universidad de Cantabria

Abstract

Forward error correction (FEC) decoding hardware modules are challenging to verify at pre-silicon stage, when they are usually described at register-transfer (RT)/logic level with a hardware description language (HDL). They tend to hide faults due to their inherent tendency to correct errors and the required simulations with a massive insertion of inputs are too slow. In this work, two verification techniques based on FPGA-prototyping are applied in order to complement the mentioned simulations: golden model vs implementation matching with thousands of random codewords and codeword/bit error rate (CER/BER) curve computation. For this purpose, a system on chip (SoC) field-programmable gate array (FPGA) is used, implementing in the programmable hardware part several replicas of the decoder (exploiting the parallel capabilities of hardware) and managing the verification by parallel programming the software part of the SoC (exploiting the presence of multiple processing cores). The presented approach allows a seamless integration with high-level models, does not need expensive testing/emulation platforms and obtains the results in a reasonable amount of time.

Highlights

T HE goal of forward error correction (FEC) components is to correct errors introduced in the channel, during transmission, in a communication system
This paper shows a proposal to perform Monte Carlo simulations of pre-silicon FEC decoders by taking advantage of the capabilities of system on chip (SoC) field-programmable gate array (FPGA)
The hardware description language (HDL) description to be verified has been recently designed for a project by the European Space Agency (ESA) following a common partial parallel architecture [16]

Summary

INTRODUCTION

T HE goal of forward error correction (FEC) components is to correct errors introduced in the channel, during transmission, in a communication system. Making the decoder testbed in hardware implies some challenging issues It has to be a translation of the original high-level model and such a task cannot always be possible or leads to a very complex HW (generation of random numbers with a good Gaussian distribution is an example). This paper shows a proposal to perform Monte Carlo simulations of pre-silicon FEC decoders by taking advantage of the capabilities of system on chip (SoC) FPGAs. The decoder is synthesized and integrated in the Programmable Logic (PL) part of a Xilinx SoC FPGA and the input generation and output checking are managed in the Processing System (PS) part by JOURNAL OF LATEX CLASS FILES, VOL.

VERIFICATION APPROACH

Decoder Integration into the Verification System

Golden Model Matching

RESULTS

CONCLUSION