Abstract
The simulated performance of a practical multithreaded mechanism for achieving high utilization of deeply pipelined (>5 stage) processors is presented. Threads are dynamically interleaved in one pipeline. After each instruction is dispatched, enough delay is introduced so that successive instructions cannot interfere. Four scheduling algorithms, three of which are realizable, are tested on a simple simulated processor. Good pipeline utilization can be achieved even when the number of running threads is less than the number of pipeline stages.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
