Practical and efficient SOC verification flow by reusing IP testcase and testbench

Abstract

The SOC verification is challenging in verifying multiple IPs' integration and on-chip inter-IP communication in the complex system. SOC Engineers have to spend tremendous efforts on learning details inside IP design, developing complex testbench and testcase for each IP, and debugging on IP internal behavior. Reusing IP verification environment in SOC verification is always a desired methodology in theory but challenging in the implementation in reality. This paper presents a practical and efficient SOC verification flow by reusing IP test bench and test case based on UVM. SOC and IP Engineers work in their own specialized area and collaborate on debugging based on SOC-IP interface. It has been successfully used in project to decrease SOC verification complexity and debugging difficulty. Efficient flow shortens the verification cycle by 2 times and reduced engineer resources by 2 times.