Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

Abstract

In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the proposed BBPD is presented. While a typical 1/N-rate BBPD uses 2N clocks for data sampling and edge tracking, the proposed 1/N rate BBPD uses only N + 1 clocks, N for data sampling and 1 for edge tracking. The power consumption of the CDR with the proposed 1/N-rate BBPD is decreased. The reduction of the jitter tracking bandwidth of the CDR is compensated by the proposed data-encoding method. The 1/10-rate PI-based CDR with the proposed BBPD is implemented using a 0.18-μm CMOS process technology. The bit error ratio of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> is achieved at the effective data rate of 6.93 Gb/s using encoded 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 pseudorandom binary-sequence data inputs. The power consumption of the CDR is 29.4 mW at the supply voltage of 1.8 V and the active area is 0.117 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The effective power efficiency of the CDR is 4.24 mW/Gb/s.