Power-limiting breakdown effects in GaAs MESFET's

Abstract

State-of-the-art GaAs MESFET'S exhibit an output power saturation as the input power is increased. Experiments indicated that this power saturation is due to the combined effects of forward gate conduction and reverse gate-to-drain breakdown. This reverse breakdown was studied in detail by performing two-dimensional numerical simulations of planar and recessed-gate FET's. These simulations demonstrated that the breakdown occurs at the drain-side edge of the gate. The results of the numerical simulations suggested a model of the depletion layer configuration which could be solved analytically. This model demonstrated that the breakdown voltage was inversely proportional to the product of the doping level and the active layer thickness.