Power-efficient and scalable virtual router architecture on FPGA

Abstract

In the recent years, networking infrastructure has advanced in such a way that router hardware management and power efficiency issues have gained considerable attention. Router virtualization alleviates these issues by allowing a single hardware router to serve packets from multiple networks. We propose a power-efficient scalable architecture for implementing router virtualization using the Virtualized Merged (VM) approach on Field-programmable Gate Array (FPGA). Three novel optimizations are incorporated into the basic VM approach to reduce the dynamic power dissipation of the router hardware and deliver higher throughput per unit power consumed. The reduction in power consumption is in part due to the savings in memory required to store the merged lookup table, which makes our optimized VM approach more scalable with respect to the number of virtual routers per FPGA chip. Also, by exploiting the low power features and clock gating techniques, the optimized VM approach achieves significant power savings. To illustrate the improvements achieved, we tested the optimized VM router using 75 routing tables on a single FPGA, utilizing 50% less memory and consuming 20% less power compared with the basic VM approach.