Abstract
This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.
Highlights
A digital-to-time converter (DTC) is similar to a digital-to-analog converter (DAC), except thatDTC converts digital values to time interval signals
DTCs are widely used in atomic frequency standards, high-precision positioning [1,2], time-correlated single-photon counting instruments (TCSPC), and measurement instruments [3,4,5,6] such as the very large scale integration (VLSI) functional tester [7]
DTCs with high resolution are mainly implemented in Application Specific Integrated Circuit (ASIC) devices, which have the of fully customized circuits and reasonably precise control of the internal propagation delay
Summary
A digital-to-time converter (DTC) is similar to a digital-to-analog converter (DAC), except that. A DTC with a resolution of 11 ps was implemented in a Xilinx Kintex-7 FPGA device based on a tapped delay line [10]. A DTC based on a Vernier ring oscillator and the Altera Stratix‐III FPGA device was proposed [5], whose theoretical resolution was 1.58 ps. DTCs with high resolution are mainly implemented in ASIC devices, which have the of fully customized circuits and reasonably precise control of the internal propagation delay. Advantages of fully customized circuits and reasonably precise control of the internal propagation it is difficult for FPGA-based DTCs to obtain high resolutions due to the additional delay introduced delay. 2. Principle of the Proposed DTC the experimental results, and Section 5 summarizes the paper
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